The SCMOS stands for super CMOS. It is basically a collection of integrated devices equipped with low-level CMOS transistors, capacitors, resistors, and diodes fabricated with iso-planary processes. However, significant differences are found in the high-level circuit configurations, device economics, dynamic circuit operations, less active nodes, and low biasing supply voltages. Thus it opens a brand new class of microelectronics, all centered around the newly added low threshold Schottky barrier diode (LSBD) with Co/Ti metal silicides. The work function of Co is 0.53 eV right in the middle of the Si electron and valence bands. So that we may form both P and N type SBDs integrate able with P or N type FETs in the extended N-/P- S/D regions.

SCMOS代表超级CMOS。 它基本上是集成电路的一件收藏器件,以基层单位之CMOS三极晶体管、电容器、电阻器和二极管, 以单向开窗法过程制造。 然而，其重大区别在于高级电路结构、设备经济效益、动态电路操作，活跃网点少, 和偏压电源低。 因而, 它开发了崭新一代之微电子产品, 围绕着最新发明的低障碍肖特基二极管(低障肖特基管). 此管(LSBD)由钴/钛金属硅化物合成。 钴/钛的功能值是0.53 eV在硅正电子和负电子带的正当中。 因此我们可能在S/D地区延伸N-/P-寄生P或N型之SBD于P或N类型FET三极晶体管之中.

Extensive Analog-Logic-Memory (ALM) applications may be created using SCMOS techniques. Wide functionality macros can be derived from the existing macro of CMOS and/or Flash transistors with the LSBD attached to the CMOS/Flash transistor source or drains. The switching diode is highly economical to build. It only costs a contact size of Si space. The forward characteristics starts logarithmic linear at 1 uA for 0.1V drop, all the way to several mA. The reverse leakages are contained in a couple nA at 5V. The author made similar SBD while he was with IBM during the 1970s using Pt/Al diodes. The barrier height was 0.7 eV, and the application was for TTL anti saturation clamps, and also made mask programmed 8kb ROM arrays with bipolar peripherals.

SCMOS技术可广泛的使用于具开创性之类比, 逻辑, 与记忆 (ALM) 电路领域.。具广阔功能之宏指令集可以从现存之CMOS和快閃晶体管宏指令集获得。低障肖特基管是具高度经济效益的，它只花费Si地区的接触点大小空间。 其正向特性, 起动于1 微安 (uA) 及0.1V偏压，以对数线性一直持续到几毫安 (mA)。 反向漏电在5V时为2奈安 (nA)。早在70年代期, 作者于IBM时,使用Pt/Al做了相似的肖特基二极管, 其障碍偏压是0.7 eV，应用为TTL反饱和钳位，并且使用双极性外圍做出了光罩编程的8000 点阵记忆体--8kb mask ROM.

The low barrier threshold (Vtd=0.1V) of the LSBD made it an ideal choice to clamp modern CMOS transistors, which has typical Vt value around 0.5V. The Vt difference between SBD and FET made it suitable to do several things efficiently. 1). Serve ESD protection for input gates. 2). Suppress transistor I-Vs, prevent well latch ups. 3). Detect Audio/Video signals. 4). Build voltage ladder charge pumps. 5). Do logic and/or or NAND/NOR trees 6). Do level shifting in I/O blocks. 7). Build, the low cost and high speed, densest storage arrays-the reachable theoretical limitation is 4F^2/bit, where F is the minimum feature size-say 0.18 um using the logic processes. 8). Perform Flash device based Binary, trinary, and quaternary computing, multiple-bit analog-to-digital (ATD)/digital-to-analog (DTA) comparators and converters.

低障肖特基管(Vt=0.1V) LSBD是一个理想的选择去截止现代CMOS 三极管. 典型的三极管Vt价值在0.5V附近。 SBD和FET之间的Vt区别, 使它能高效率地做几件事。 1).为输入閘门作静电保护-ESD。 2). 压制晶体管特性，防止电路死锁。 3). 音频或视频信号整流器。 4). 修造电压梯子灌注泵。 5). 做逻辑与非/或非閘门树-NAND/NOR tree. 6)。在输入/输出块作升降压转换。 7). 研发最便宜和高速，最密集的存贮器-其可达之理论极限为每比特佔 4F平方空间. F是IC器件上之最小间距譬如说0.18 微米(um)。 8). 执行快閃晶体电路中二层次 (Binary)，三层次 (Ternary) 和 四层次 (quaternary) 进制之运算，多位比特之类比/数码信号交换器.

Most importantly, we keep on finding useful traits of the LSBD for it exhibits the finest switching and analog properties with simplicity and efficiency built-in. Process wise, it is attached to the FET transistors with minimum deviation only in contact metal treatments, and sub-region resistance implant as options to lower the cathode/anode resistances when performance requires.

最重要，我们能继续发现LSBD有用的特征. 因为它以简单而又有效的方式陈现了最佳的开关和类比功能。 在上百个制程步鄹方面, 它可寄生于FET三极管制程之中,仅以最小偏差在硅
体/接触金属操作时, 加以修改. 在優化功能的考究下, 植入离子用以选择性的降低二极管之负极或阳极电阻。

Circuit/layout wise, the LSBD is a cute little piece circuit element-the smallest entity of any integrated components with common anode or common cathode bed sharing with the FET transistor source or drain nodes. Because the newly defined Schottky CMOS logic (SCL) is composed of a tiny dynamically operated I-source with branching diode trees, it greatly simplified the TTL logic circuitry with greatly reduced on-chip 1).total net counts(to 1/3 rd), 2).active net counts (to 1/3 rd), 3). transistor counts, and 4). Parasitic pocket counts. The result is that 5). logic switching signal is much cleaner, and much faster. Power-Speed trade off with 6). gigantic TTL nets disappeared, the replaced DTL nets are both reduced in active net counts, and 7). lowered associated RC time constants (i.e., inverters driving smaller pockets and wiring pitches comparing with TTL nets).

电路或布局方面， LSBD是所有集成电路的基层单位一逗人喜爱的小片断电路元素。这是世上最小的开关, 与FET三极管之源极共享一个阳极或阴极接触点。 由于此最新被定义的肖特基CMOS逻辑电路(SCL)是由一个微小的动态电源与分支的二极管树所组成，它大大地简化了傳統TTL在片逻辑电路1). 总的網点计数(减至1/3), 2). 具减少的活跃網点计数、3). 三极管计数和 4). 寄生口袋计数。 结果是5). 逻辑开关信号是更加干净和快速, 6). 功耗量硕大的TTL网路消失了，取而代之的是精细的DTL网路, 其伴生的7). RC时间常数下降了,活跃之网点计数和相关的RC常数都大幅下降 (和TTL网路相比，所有网点都是由反向器来驱动更小的口袋和布线)。

Now that we get simple inverters driving DTL stages everywhere, the power supply, required by SCL, may be dropped to just above the FET threshold Vt ( say ~0.6V).  In general, on chip power consumption for any net is proportional to the square of the supply voltage and ac currents. If Vsupply lowers to ½, power reduction shall reduces to ¼. The SCL has significantly smaller layout areas; parasitic capacitances with wirings and pockets, hence the power advantage is more than 4X. This would not be possible to achieve with conventional CMOS TTL circuitry since it has inherently topological and structural disadvantages.

现在, 既然我们到处得到反向器来驱动所有网点，SCL电源可以放心下降至略高于FET三极管之Vt (约~0.6V)。一般来说，所有网点之在片功耗量为其电源电压或ac电流的平方成正比。 如果Vsupply降下½，功耗将减少到¼。 SCL有显着更小的布局间距; 接线和口袋之寄生电容，因此功耗将减少比4倍更多。常规之CMOS TTL电路, 因为它有固有的拓扑学和结构上的缺点，这是不可能达到的。

The embedded memory arrays include high density, high speed Mask ROM, OTP (One-time-Programmable) ROM, SRAM, DRAM, EEPROM, single-level-cell (SLC) Flash, and mult-level-cell (MLC) Flash entities. Flash device is denser than DRAM but is slow. The LSBD may serve in the core array cells as in the case of 6TSRAM, Mask ROM, and OTP ROM macros. The latter two implementations shall have triple benefits with densest arrays ; basically low cost processes and being single contact/bit), fast speed, and low power consumption.

嵌入式记忆列阵包括高密度，高速之光罩编程的点阵记忆体(mask programmed ROM)、OTP (一次性可编程序记忆体) ROM、静忒记忆体6TSRAM、动忒记忆体 DRAM、电子更改记忆体EEPROM、单一狀忒(二层次) 快閃晶体管 (SLC), 和多层次快閃晶体管(MLC)。 快閃晶体管比动忒记忆体便宜但是太慢. 低障肖特基管LtSBD可作为核心矩阵服务,取代傳統之6TSRAM、Mask ROM和OTP ROM等宏指令库。 后者二种施工将有3个重大贡献;基本上便宜的制程,快速和低功耗.

Wide piggy bag benefits to all memory and processor devices

各类记忆体及处理机之外快好处

The SCL peripherals may also be employed to enhance array (DRAM, Flash) for gaining speed, density, and power efficiency. Different kind of memory speeds ranked from SRAM (nS), DRAM, ROM (10s nS), Flash (uS) while storage areas go to the opposite direction.  Notmally, transistor ROMs (and EEPROM/Flash devices) were considerably slower than RAMs. However, due to area reduction, fast SBD circuits, and Vsupply reduction, the SCMOS ROMs, SCL wrapped DRAM, Psuedo 6TSRAM, SCL wrapped Flash arrays, and 4T-SRAM (by SCMOS) shall claim all advantages one can ever dream of.

SCL外围设备也可被使用于提高列阵(动忒记忆体，快閃电路)之功能;为获取速度、密度和提升功耗效率。 各类记忆体之速度依次为SRAM 奈秒级(nS)， DRAM10奈秒级(10 nS)， ROM，Flash 微秒级(uS)，而贮存密度去反向正好相反。  一般地说，三极管ROMs (加上EEPROM/Flash设备) 比(SRAM/DRAM)可观地慢。 然而，由于实际面积减少、快速的SBD电路和Vsupply降低、SCMOS ROMs和SCL包裹后的DRAM, Psuedo 6TSRAM电路，SCL包裹后的 快閃电路， 和由SCMOS做的4T-SRAM将能达到你可能梦想的所有好处。

SBD ROM may have huge on-chip control store and fast cycle times for fast state machine in search engines for BIOS routines, games/DNA codes, Letters, images, and audio storage, and BIST (build-in-sef-test) programs. It may replace functions of conventional SRAM (near nS) and exceed conventional DRAM (10s of nS), and Flash devices (uS) in power-speed and cost considerations.

SBD ROM具大量的内存,及快速之在片读出周期, 可用之于处理机之基本系统操作码, 游戏机控制码, 文字图画音像储存, 基因識別码, 内存测试码修造自备测试 (BIST). 在速度功耗和成本的考量上, 它们可以取代那些常规6TSRAM (奈秒级nS), 并/超越常规的DRAM(10s of nS), 和Flash (微秒uS) 设备。

The SCMOS chips shall continue Moore’s law with improved DTL circuit topology and simplified SCL circuits, which are without the expensive and stacked TTL legs; all CMOS TTL nets with more than 2 way input gates are replaced. Thus, supply voltage and on/off chip signal swings may be substantially lowered. One can expect all the nice features (density, speed, power, and field programmability) with the emerging SCMOS implementations.

SCMOS芯片将持续摩尔定律Moore’s law, 用被改进的DTL电路拓扑结构和被简化的SCL电路. 此方案中没有昂贵的和被堆积的TTL大腿; 所有CMOS TTL网路其超过2进输入以上之逻辑电路都被替换。 因此，电源电压和开关芯片信号振幅大大地被下降。你可期望, SCMOS的各类实施不断涌现, 新一代的IC具备所有好的特点(密度、速度、功耗和现场可编程序性)。

Two US core patents were granted for SCMOS circuits and methods.  (For patent research please click www.uspto.org)  

SCMOS电路和方法被授予了二个美国核心专利。  (请点击www.uspto.org)

US Pat. 6,852,578 – Filed January 15, 2003, and

美国专利. 6,852,578 –2003年1月15日归档，和

US Pat. 6,590,800 – Filed June 15, 2001

美国专利. 6,590,800 –2001年6月15日归档

Many other children patents were filed for the proliferated ASIC/generic applications with RAM and ROM, SLC/MLS Flash devices, analog, and wired/wireless infra-structural implementations. Many chip process, hardware, and software means for multi-level computing are claimed.

许多其他子专利为激增的專用集成电路和一般应用,被归档于以RAM和ROM， SLC/MLS Flash设备，类比电路,有线的或无线的基础建设实施。 许多为多层运重计算芯片制程，硬件，软件手段等都被归档。

The SCMOS solution shall offer a powerful design platform for the 5th generation microchips. We have opened new practices that diodes replace transistors as the massive switching elements and core arrays, and the dynamical low power nets manage precisely over-all chip power consumptions, and multi-level, in addition to binary computing, starts with the finest diode threshold divisions. 

SCMOS方案将为第5世代集成电路芯片提供一个强有力的设计平台。我们开创了崭新的实践以二极管替换三极管作为主流的开关元素和核心矩阵，并且动态低功耗网路精确地处理整体芯片之电力消费，和多层次进制-开創了除二进制运算之外，以最精细的二极管障压为準的电压分裂法則。

The SCMOS drives with ease physical size and electrical signal scale-downs, setting new records and trends for low power, high performance microelectronics on a new chapter. And I believe it shall emerge, after copper conductor and Flash technology, as the new tramp cards for mainstream SoC solutions. It shall serve as vital alternatives to continue Moore’s law with CMOS TTL. Leaders in world class foundries and IP developers ought to seriously consider it for generic applications, special payoff is expected for personal mobile communication and multi-level signal processing.

SCMOS将在一个新的章节里容易地驾驭物理尺寸趋小和电信号振幅下降,设置新纪录和趋向,为低功耗，高性能之微电子研制出产品。 并且我相信它将在继铜导线和快閃晶体管技术之后涌现，为主流SoC芯片组合提供王牌解答。 它将继续推进Moore定律,并成为传统CMOS TTL工艺以外之重要选择。具国际水平的流片厂和智慧財产开发商之领导层,应该慎重考虑它作为一般应用，个人移动通信和多层次資訊之操作将获特别好的发展。